FPGA Implementation of SC-FDE Timing Synchronization Algorithm


Suyuan Ji, Chao Chen, Yu Zhang, Journal of Information Processing Systems Vol. 15, No. 4, pp. 890-903, Aug. 2019  

https://doi.org/10.3745/JIPS.04.0127
Keywords: FPGA Implementation, SC-FDE, Timing Synchronization
Fulltext:

Abstract

The single carrier frequency domain equalization (SC-FDE) technology is an important part of the broadband wireless access communication system, which can effectively combat the frequency selective fading in the wireless channel. In SC-FDE communication system, the accuracy of timing synchronization directly affects the performance of the SC-FDE system. In this paper, on the basis of Schmidl timing synchronization algorithm a timing synchronization algorithm suitable for FPGA (field programmable gate array) implementation is proposed. In the FPGA implementation of the timing synchronization algorithm, the sliding window accumulation, quantization processing and amplitude reduction techniques are adopted to reduce the complexity in the implementation of FPGA. The simulation results show that the algorithm can effectively realize the timing synchronization function under the condition of reducing computational complexity and hardware overhead.


Statistics
Show / Hide Statistics

Statistics (Cumulative Counts from November 1st, 2017)
Multiple requests among the same browser session are counted as one view.
If you mouse over a chart, the values of data points will be shown.




Cite this article
[APA Style]
Ji, S., Chen, C., & Zhang, Y. (2019). FPGA Implementation of SC-FDE Timing Synchronization Algorithm. Journal of Information Processing Systems, 15(4), 890-903. DOI: 10.3745/JIPS.04.0127.

[IEEE Style]
S. Ji, C. Chen, Y. Zhang, "FPGA Implementation of SC-FDE Timing Synchronization Algorithm," Journal of Information Processing Systems, vol. 15, no. 4, pp. 890-903, 2019. DOI: 10.3745/JIPS.04.0127.

[ACM Style]
Suyuan Ji, Chao Chen, and Yu Zhang. 2019. FPGA Implementation of SC-FDE Timing Synchronization Algorithm. Journal of Information Processing Systems, 15, 4, (2019), 890-903. DOI: 10.3745/JIPS.04.0127.